Local and global planarization of semiconductor wafers becomes increasingly important as more metal layers and interlayer dielectric layers are stacked on the wafers. A preferred method to planarize semiconductor wafers is the chemical mechanical polishing (CMP) method, where a surface of a semiconductor wafer is polished using a slurry solution supplied between the wafer and a polishing pad. The CMP method is also widely used for damascene process to form copper structures on the semiconductor wafers.
In general, a CMP equipment includes a polishing table where a polishing pad is placed and a wafer carrier that supports a semiconductor wafer and presses the wafer against the polishing pad. One of the most important performances of a CMP equipment is productivity. For higher productivity, a CMP equipment typically requires more polishing tables and more wafer carriers. As the number of polishing tables and wafer carriers included in a CMP equipment is increased, the arrangement of the polishing tables and the wafer carriers becomes important to efficiently polish multiple semiconductor wafers. Furthermore, the manner in which the semiconductor wafers are transferred to and from the wafer carrier becomes important as well. However, the footprint of a CMP equipment must also be considered since a CMP equipment with a large footprint requires a larger clean room to house the equipment, which translates into greater cost of operation.
In view of these issues, what is needed is an apparatus and method for polishing semiconductor wafer using multiple polishing tables with high productivity that require small footprint.